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Features
* Incorporates the ARM7TDMITM ARM(R) Thumb(R) Processor Core
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-Circuit Emulation) 4K Bytes Internal RAM Fully-programmable External Bus Interface (EBI) - Maximum External Address Space of 64M Bytes - Up to Eight Chip Selects - Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller - 4 External Interrupts, Including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter - Three External Clock Inputs - Two Multi-purpose I/O Pins per Channel Two USARTs - Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Low-power Idle Mode Fully Static Operation: 0 Hz to 33 MHz 2.7V to 3.6V Operating Range -40C to 85C Operating Temperature Range Available in a 100-lead TQFP Package
* *
* * * * * * * * * *
AT91 ARM(R) Thumb(R) 16/32-bit Microcontroller AT91M40400 Electrical and Mechanical Characteristics
Description
The AT91M40400 is a member of the Atmel AT91 16/32-bit microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based microcontroller unit family also features Atmel's highdensity, nonvolatile memory technology. The on-chip Flash program memory is insystem programmable. The AT91M40400 has a direct connection to off-chip memory, including Flash, through the External Bus Interface (EBI). The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip RAM and a wide range of peripheral functions on a monolithic chip, the AT91M40400 is a powerful microcontroller that offers a flexible, cost-effective solution to many compute-intensive embedded control applications.
Rev. 1078C-12/00
1
Pin Configuration
Figure 1. AT91M40400 Pinout (Top View)
P21/TXD1/NTRI
P15/RXD0
P20/SCK1
P13/SCK0
P14/TXD0
P6/TCLK2
P3/TCLK1
P8/TIOB2
P7/TIOA2
P11/IRQ2
P10/IRQ1
P12/FIQ
P5/TIOB1
P9/IRQ0
P4/TIOA1
GND
P18
75
74
73
P19
72
71
P17
70
P16
69
68
67
66
65
64
63
62
VDD
61
VDD
60
59
58
57
56
55
54
53
GND
52
P27/NCS3 P26/NCS2 NCS1 NCS0 NWAIT VDD VDD NWR0/NWE NRD/NOE TCK TDO TDI TMS GND GND P25/MCKO P24/BMS P23 MCKI VDD NWDOVF NRST GND NWR1/NUB P22/RXD1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 3 4 5 6 7 8 1 9
51
P2/TIOB0
GND
26 27 28 29 30 31 32 33 34 35 36 37
P29/A21/CS6 VDD VDD P30/A22/CS5 P31/A23/CS4 D0 D1 D2 D3 D4 GND D5 D6 D7 D8 D9 D10 D11 VDD D12 D13 D14 D15 P0/TCLK0 P1/TIOA0
AT91M40400 100-lead TQFP
38 39 40 41 42 43 44 45 46 47 48 49 50
A19
2
AT91M40400
P28/A20/CS7
A16
GND
A0/NLB
GND
GND
A11
A12
VDD
A10
A13
A14
A15
A17
A18
A5
A6
A1
A2
A3
A4
A7
A8
A9
AT91M40400
Table 1. AT91M40400 Pin Description
Module Name A0 - A23 D0 - D15 NCS0 - NCS3 CS4 - CS7 NWR0 NWR1 EBI NRD NWE NOE NUB NLB NWAIT BMS FIQ AIC IRQ0-IRQ2 TCLK0-TCLK2 Timer TIOA0-TIOA2 TIOB0-TIOB2 SCK0-SCK1 USART TXD0-TXD1 RXD0-RXD1 PIO WD Clock MCKO NRST Reset NTRI TMS TDI ICE TDO TCK VDD Power GND Ground Test Data Output Test Clock Power Output Input - - Schmidt trigger, internal pull-up Tri-state Mode Select Test Mode Select Test Data Input Input Input Input Low - - Sampled during reset Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Master Clock Output Hardware Reset Input Output Input - Low Schmidt trigger, internal pull-up P0-P31 NWDOVF MCKI External Interrupt Request Timer External Clock Multipurpose Timer I/O Pin A Multipurpose Timer I/O Pin B External Serial Clock Transmit Data Output Receive Data Input Parallel IO Line Watchdog Overflow Master Clock Input Input Input I/O I/O I/O Output Input I/O Output Input - - - - - - - - Low - Open drain Schmidt trigger PIO - controlled after reset PIO - controlled after reset PIO - controlled after reset PIO - controlled after reset PIO - controlled after reset PIO - controlled after reset PIO - controlled after reset Function Address Bus Data Bus Chip Select Chip Select Lower Byte 0 Write Signal Upper Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select Lower Byte Select Wait Input Boot Mode Select Fast Interrupt Request Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Active Level - - Low High Low Low Low Low Low Low Low Low - - Sampled during reset PIO - controlled after reset A23 - A20 after reset Used in Byte Write Option Used in Byte Write Option Used in Byte Write Option Used in Byte Select Option Used in Byte Select Option Used in Byte Select Option Used in Byte Select Option Comments All valid after reset
3
Absolute Maximum Ratings*
Operating Temperature (Commercial) ........0 to +70C Operating Temperature (Industrial) .....-40C to +85C Voltage on any input Pin with respect to Ground ........................-0.5V to +5.5V Maximum Operating Voltage ................................4.6V DC Output Current ..............................................2 mA
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
TA = -40C to 85C, VDD = 2.7V to 3.6V unless otherwise specified. All pads are 5V tolerant. Table 2. DC Characteristics
Symbol VIL VIH VOL VOH IOH IOL ILEAK IPULL ICAP ISC Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Source Current Output Sink Current Input Leakage Current Input Pull-up Current Input Capacitance for all Pins Static Current VDD = 3.6V, MCKI = 0 Hz All inputs driven, TMS, TDI, TCK, NRST = 1 30 Condition Min -0.5 0.7 x VDD Typ Max 0.3 x VDD VDD + 0.5 or 5.5 0.1 Units V V V V 2 2 100 mA mA nA A pF A
VDD = 2.7V to 3.6V
VDD = 2.7V to 3.6V IOL = 0.8 mA, VDD = 3.0V IOH = 0.8 mA, VDD = 3.0V
VDD - 0.1
VDD = 3.0V, VOH = 2.4V VDD = 3.0V, VOL = 0.4V VDD = 3.3V, VIN = 0
-400
-80 12
4
AT91M40400
AT91M40400
Power Supply Current
The following table shows results of measurements peformed at typical conditions (VDD = 3.3V and TA = 25C). Table 3. Power Consumption
Mode Reset Normal Idle Conditions NRST = 0 Fetch in Internal SRAM - Typ 1.08 1.42 0.63 Unit mW/MHz mW/MHz mW/MHz
Conditions
Environment Constraints
The output delays are valid for a capacitive load of 50 pF as shown in Figure 2. Figure 2. Output/Bi-directional Pad Capacitive Load
CL = 50 pF PAD
Timing Results
The output delays are for a capacitive load of 50 pF as shown in Figure 2 above. In order to obtain the timing for other capacitance values, the following equation should be used: t = t datasheet + ""factor x ( C load - 50 pF ) Table 4. Derating Factor Due to Capacitive Load Variation
Parameter Factor Commercial 0.052 Industrial 0.058 Units ns/pF
5
Clock Waveforms
Table 5. Clock Waveform Parameters
Minimum Symbol 1/tCP tCP tCH tCL tr tf Parameter Oscillator Frequency Main Clock Period High Time Low Time Rising Edge Falling Edge 40 17 17 30 12 12 TBD TBD TBD TBD 25 MHz 33 MHz 25 MHz 25 Maximum 33 MHz 33 Units MHz ns ns ns ns ns
Table 6. Clock Propagation Times
Maximum Symbol tCDLH tCDHL Parameter Rising Edge Propagation Time Falling Edge Propagation Time 25 MHz 12 12 33 MHz 9 9 Units ns ns
Figure 3. Clock Waveform
tCH tr tf
MCKI
0.3 VDDIO
0.7 VDDIO tCL
tCP
MCKO
tCDLH tCDHL
6
AT91M40400
AT91M40400
AC Characteristics
The following tables refer to Figure 4. Table 7. General-purpose EBI Signals
Minimum Symbol EBI1 EBI2 EBI3 EBI4 EBI5 EBI6 EBI7 Parameter MCKI Falling to NUB Valid MCKI Falling to NLB/A0 Valid MCKI Falling to A7 - A1 Valid MCKI Falling to A23 - A8 Valid MCKI Falling to Chip Select NWAIT Setup before MCKI Rising NWAIT Hold after MCKI Rising 25 MHz 4 6 6 6 5 4 1 33 MHz 4 6 6 6 5 4 1 Maximum 25 MHz 16 22 22 21 21 8 5 33 MHz 11 14 15 14 14 6 4 Units ns ns ns ns ns ns ns
Table 8. EBI Write Signals
Minimum Symbol EBI8 EBI9 EBI10 EBI11 EBI12 EBI19 EB20 EBI21 EBI22 EBI23 Parameter MCKI Rising to NWR Active (No Wait States) MCKI Rising to NWR Active (Wait States) MCKI Falling to NWR Inactive (No Wait States) MCKI Rising to NWR Inactive (Wait States) MCKI Rising to D0 - D15 Out Valid NWR High to A23 - A1, NUB/NLB/A0, NCS, CS changes (No Wait States) NWR High to A23 - A1, NCS, CS Changes (Wait States) Data Out Valid before NWR High Data Out Valid after NWR High (No Wait States) Data Out Valid after NWR High (Wait States) 25 MHz 3 3 4 4 5 TBD tCP/2 TBD TBD tCP/2 33 MHz 3 3 4 4 5 TBD tCP/2 TBD TBD tCP/2 Maximum 25 MHz 14 14 16 16 20 33 MHz 10 10 11 11 14 Units ns ns ns ns ns ns ns ns ns ns
7
Table 9. EBI Read Signals
Minimum Symbol EBI13 EBI14 EBI15 EBI16 EBI17 EBI18 Notes: Parameter MCKI Falling to NRD Valid(1) MCKI Rising to NRD Valid
(2)
Maximum 25 MHz 15 15 3 2 33 MHz 10 10 3 2 Units ns ns ns ns ns ns
25 MHz 4 4 2 1 TBD TBD
33 MHz 4 4 2 1 TBD TBD
D0 - D15 in Setup before MCKI Falling D0 - D15 in Hold after MCKI Falling NRD High to A23 - A1, NCS, CS Changes Data Hold after NRD High 1. Early Read Protocol 2. Standard Read Protocol
8
AT91M40400
AT91M40400
Figure 4. EBI Signals Relative to MCKI
MCKI EBI5 EBI5
NCS
CS EBI3/EBI4 A1 - A23 EBI6 NWAIT EBI7
No Wait
Wait
EBI1/EBI2 NUB/NLB/A0 EBI13
EBI13
EBI17
NRD(1) EBI14 NRD(2) EBI15 EBI16
EBI18
D0 - D15 read EBI8 NWR (No Wait States) EBI9 NWR (Wait States) EBI12 EBI21 EBI22 EBI22 EBI11 EBI20 EBI10 EBI19
D0 - D15 to Write No Wait Wait
Notes:
1. Early Read Protocol 2. Standard Read Protocol
9
Peripheral Signals
USART Signals The inputs have to meet the minimum pulse width and period constraints shown in Table 10 and Table 11, and represented in Figure 5. Table 10. USART Input Minimum Pulse Width
Symbol US1 Parameter SCK/RXD Minimum Pulse Width Minimum Pulse Width 3(tCP/2) Units ns
Table 11. USART Minimum Input Period
Symbol US2 Parameter SCK Minimum Input Period Minimum Input Period 5(tCP/2) Units ns
Figure 5. USART Signals
US1
RXD US2 US1 SCK
10
AT91M40400
AT91M40400
Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total Count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Tables 12 and 13, and as represented in Figure 6. Table 12. Timer Input Minimum Pulse Width
Symbol TC1 Parameter TCLK/TIOA/TIOB Minimum Pulse-Width Minimum Pulse Width 3(tCP/2) Units ns
Table 13. Timer Input Minimum Period
Symbol TC2 Parameter TCLK/TIOA/TIOB Minimum Input Period Minimum Input Period 5(tCP/2) Units ns
Figure 6. Timer Input
3(tCP/2) TC2 1(tCP)
MCKI TC1 TIOA/TIOB/TCLK
11
Watchdog Timer Signals Table 14. Watchdog Timer Outputs
Minimum Symbol WD1 WD2 Parameter MCKI Rising to NWDOVF Rising MCKI Rising to NWDOVF Falling 25 MHz 3 4 33 MHz 3 4 Maximum 25 MHz 13 14 33 MHz 9 ns 10 Units
Figure 7. Watchdog Signals Relative to MCKI
MCKI
WD1 NWDOVF Output Z
WD2 Z
Reset Signals A minimum pulse width is necessary, as shown in Table 15 and as represented in Figure 8. Table 15. Reset Minimum Pulse Width
Symbol RST1 Parameter NRST Minimum Pulse Width Minimum Pulse Width 10(tCP) Units ns
Figure 8. Reset Signal
RST1 NRST
Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous.
12
AT91M40400
AT91M40400
Advanced Interrupt Controller Signals Inputs have to meet the minimum pulse width and mimimum input period shown in Table 16 and Table 17 and represented in Figure 9. Table 16. AIC Input Minimum Pulse Width
Symbol AIC1 Parameter FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width Minimum Pulse Width 3(tCP/2) Units ns
Table 17. AIC Input Minimum Period
Symbol AIC2 Parameter AIC Minimum Input Period Minimum Input Period 5(tCP/2) Units ns
Figure 9. AIC Signals
AIC2 MCKI
AIC1 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Input
13
Parallel I/O Signals The inputs have to meet the minimum pulse width shown in Table 18 and represented in Figure 10. Table 18. PIO Input Minimum Pulse Width
Symbol PIO1 Parameter PIO Input Minimum Pulse Width Minimum Pulse Width 3(tCP/2) Units ns
Figure 10. PIO Signal
PIO1 PIO Inputs
14
AT91M40400
AT91M40400
ICE Interface Signals Table 19. ICE Interface Timing Specifications
Minimum Symbol ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 Parameter TCK Low Period TCK High Period TDI, TMS Setup to TCK TDI, TMS Hold from TCK TDO Hold Time TCK to TDO Valid TBD TBD TBD TBD TBD TBD TBD TBD 25 MHz TBD TBD 33 MHz TBD TBD TBD TBD ns Maximum 25 MHz 33 MHz Units
Figure 11. ICE Interface Signal
TCK ICE1 ICE2
TMS/TDI ICE3 ICE4
TDO ICE5 ICE6
15
Package Outline TQFP 100
100-lead Thin (1.4 mm) Quad Flat Pack
Table 20. Common Dimensions (mm)
Symbol c c1 L L1 R2 R1 S q 0.08 0.08 0.2 0 0 11 11 12 12 13 13 1.6 0.05 1.35 1.4 0.15 1.45 3.5 7 Min 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.2 0.16 0.75
1 2 3
A A1 A2
Tolerances of form and position aaa bbb 0.2 0.2
Table 21. Lead Count Dimensions
Pin Count 100 D/E BSC 16.0 D1/E1 BSC 14.0 b Min 0.17 Nom 0.22 Max 0.27 Min 0.17 b1 Nom 0.2 Max 0.23 e BSC 0.50 ccc 0.10 ddd 0.06
Thermal resistance of package: 40C/W.
16
AT91M40400
AT91M40400
Figure 12. 100-lead TQFP Package Drawing
aaa
bbb
PIN 1
2 S
ccc
3 ddd
R1
1
R2
0.25
c
c1 L1
17
Ordering Information
Speed (MHz) 25 33 Power Supply 2.7V to 3.6V 2.7V to 3.6V Ordering Code AT91M40400-25AI TQFP 100 AT91M40400-33AC Commercial (0C to 70C) Package Operation Range Industrial (-40C to 85C)
18
AT91M40400
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(c) Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Limited. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper.
1078C-12/00/0M

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